Reconfigurable software development

We use a fixed set of pro- and outs and ins are lists of output and input variables. Then cessor registers to pass the inputs to the instruction simu- the C simulation model follows.

Two special instructions are defined to support the simu- The source code annotated with pragma directives is lation: then processed to generate a new C program, where two tofpga saves the current state of the processor registers to assembler macros are defined, one to be used to generate a shadow register file, and passes its arguments in- code for the target architecture, the other to be used to gen- puts of the PiCoGA-based instruction to the emula- erate code for the simulator to emulate the PiCoGA behav- tion function.

It also stops cycle counting while emu- ior. The macro defined for the target architecture is very lating the PiCoGA instruction. On the other hand, the macro for the simulation model then restores the registers from the shadow register file. DES encryption Table 1. Speed-ups for several signal pro- 4.

In fact, instruction memory the PiCoGA. On the Assuming that the processor never stalls, since most haz- other hand several tests showed that access to data memory ards can be already resolved at compilation time, it is nor- roughly scales with speed-up too.

In fact, the execution on mally sufficient to increment the cycle count at each instruc- pGA allows an improved efficiency for data management tion that is simulated.

However in the case of PiCoGA in- e. Figure 6 shows how XiRisc proces- of the value returned in a predefined register by their em- sor, enhanced by the pGA, achieves energy consumption ulation code. This is achieved by stopping the clock in in- reduction. Finally we developed a simple pro- 6 Conclusions filer which takes execution traces provided by the simulator as input and generates the following information: A new reconfigurable processor, together with a software development tool chain has been presented.

This paper illustrates the main design de- ent instruction opcode. We implemented general-purpose data-intensive al- gorithms using the design flow discussed, and we applied all the speed-up optimizations by hand. Achieved speedups 5 Results range from 4.

Table 1 shows speedups achieved of the References implemented reconfigurable processor, calculated counting the number of execution cycles with respect to those of the [1] Tensilica Inc.

Power consumption is the other key issue. For classi- [2] P. Athanas and H. Processor reconfigu- cal processor-based architectures, the main source of power ration through instruction-set metamorphosis.

IEEE consumption is due to memory access. Measurements on a Computer, 26 3 —18, March Razdan and M. Since every tional units. In Proceedings of the 27th Annual Inter- clock cycle a new instruction is fetched, the only way to re- national Symposium on Microarchitecture, November duce instruction memory energy consumption is to reduce Normalized energy consumption for some signal processing algorithms [4] Z.

Ye, N. Shenoy, and P. In Programmable Custom Computing Machines ,pp. Hauck, K. Compton and Z. Wittig, and P. In Proceedings of ,pp. Lavagno, C. GA-op is described using a pragma directive: pragma p. GA-op 0 x Sofware Simulation Two special instructions are defined to support emulation:. Function clock cycle count is halted n fmpga copies emulation function result s and restores registers; cycle count is incremented with the latency value of the p.

GA-op Evaluation of overall performances by counting elaboration cycles. Conclusions n Xi. GA: pipelined, runtime configurable, row-oriented array of LUT-based cells n Specific software development toolchain n Speedups range from 4.

Processor Datapath and Control Single cycle processor Datapath. Processor Design 5 Z Processor Datapath and. Architecture , 3 , 2. Cluster Computing , — Kienhuis, B. A methodology to design programmable embedded systems pp. Berlin, Heidelberg: Springer. Acceleo-transforming models into code.

Karray, F. Earnpipe: A testbed for smart water pipeline monitoring using wireless sensor network. Procedia Computer Science, 96, — Polley, J. In IEEE communications society conference on sensor and ad hoc communications and networks. Wsnet overview. Accessed: June Ns-2 the network simulator.

A simulation model for wireless sensor networks based on tossim. Adib, R. Castalia network animator cna : A visualization tool for castalia wireless sensor network simulator. In Ninth international conference on information technology—New generations. Varga, A. Download references.

You can also search for this author in PubMed Google Scholar. Correspondence to Raoudha Saida. Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations. Reprints and Permissions. A model based process for reconfigurable wireless sensor network development. Wireless Netw Download citation. The processes are performed by a single group as shown in Fig.

Hence, a substantial amount of the design and next two sections. From Table 1 it is clear that if button 2 is pressed, QPSK Design, Modulation will be chosen and the transmitter will transmit Implementation, Production the bits using this modulation scheme.

When none of the buttons is pressed, the transmitter will transmit BPSK signal. And Testing As shown in Fig. From the ADC onwards it is the receiver part. This will be taken up in the next section which describes the demodulator. The next block is ADC which comes under the receiver section which is the next section to be discussed. From Fig. To generate the cosine and sin signals, two Direct Digital Synthesizers DDS are employed in the design of the system, one for the cosine and one for the sine.

The various amplitude values for the various modulation schemes are depicted in Table 2. In all there are 8 bits per symbol in the QAM modulation scheme. Since this circuit follows gray coding, the amplitude values are not in order. This is depicted in Table 3. Table 2. The receiver takes 64 samples to decide which modulation scheme is transmitted.

After the decision taken, the corresponding demodulated signal is fed to the detector for detection. Hence, after the detection process, the generated 6.

The power select block calculates the interleaver. After this process the resultant bit word is fed power of the incoming signal by squaring each sample to the Block Decoder which strips off the redundant 32 bits received and then summing them up after 64 samples are and makes necessary bit corrections to give a bit word.

This is depicted in Equation 1. This is fed to the speakers for listening. Both these processes are executed from Simulink Environment.